Partial Fulfillment of the Requirement for the BSEE Degree, Electrical and
Systems Engineering Department, School of Engineering and Applied Science,
Washington University in St. Louis
The designers have applied ethics in the design process and in selection of the final design. We the designers have complied with the WUSTL Honor Code.
We designed an ASIC CMOS circuit to use a
smartphone’s audio output to power an integrated circuit at 1.8 V and 2 mA in
the ami0.6 process. The design works on a range of smartphones using iOS and
Android operating systems taking into account their varying power outputs at an
efficiency of 37.3%. The design can fit on a 1mm x 1mm die with two 2µF and two
1µF capacitors off chip as well as 4 resistors to set up feedback voltage and
to properly operate our voltage regulator. There are 3 main phases to the
design: rectification, voltage boosting, and voltage regulation.
We would like to acknowledge Dr. Robert Morley for his assistance and advice throughout the design process.
Figure : Square wave composed of 1, 3, and 5 harmonics.
Design a circuit to use the audio output of a phone to power an integrated circuit at 1.8 V and 2 mA. Further, we restricted ourselves to building the design as an ASIC in ami0.6 technology with as little off-chip parts as possible in order to differentiate our design from similar existing circuits. The design should work on as many existing smartphones as possible, emphasizing Android and iOS smartphones.
There are two inputs into the system, a left and
right channel of the audio output from the phone. The two inputs are 180˚
out-of-phase 4 kHz square waves with a peak-to-peak voltage in the range from
1-2 volts. We chose a square wave because it has the maximum RMS voltage and can
therefore transfer the most power. We used 4 kHz because if we went any
lower then our capacitors would need to be much larger to provide the right
amount of current. Any higher square wave frequency would not have the fifth or
greater harmonic as the phones could only output up to 20 kHz. Therefore 4 kHz
provided maximum power while minimizing capacitor sizing. Figure 1 is an image
of what our 4 kHz wave looks like.
The original design consisted of two main parts: rectifier and voltage regulator. The plan was to convert the two inputs into positive and negative DC components and then to regulate down the difference in voltage to the desired 1.8 V. We soon found out that some phones have a maximum voltage output of less than 1.8 V, so we decided that it would be necessary to boost the voltage is some way in order to allow our device to work on said phones. An early plan for rectification and voltage boosting was to use a voltage multiplier that would rectify and boost at the same time, but papers for these designs showed that they wouldn’t be able to output enough current. A different solution was to fully rectify first and then boost the voltage. We found a paper about a fully on chip rectification circuit that worked for us and would use only 4 transistors. The drop in voltage across the rectifier was a couple millivolts so we went with this plan. This still left us with a need to boost the voltage somehow.
Our search for voltage boosters found two competing ideas, the charge pump and the switch capacitor. The switch capacitor was selected because of the higher efficiency in testing and available current at the output. Our research into the charge pump would prove helpful though as it was needed later to boost the voltage of our control lines, which we soon found to be needed. We were trying to boost the line voltage higher than the gate voltages on the component transistors. The charge pump was selected as the ideal voltage booster for the controls because of the low current draw and its efficiency at increasing voltages.
The outputs from the charge pump were DC lines, instead of the clocks we wanted. A two-inverter amplifier was designed in which the boosted voltage would be the power source and the initial low voltage oscillating input would drive the inverter. It turned out that the first inverter was drawing too much power so we added high impedance to the first inverter stage that would reduce the power draw. To compensate, for this loss of a useful inverter we added a third inverter to drive the controls.
The voltage regulator proved to be the most time consuming stage of the design. We implemented a working regulator early on, but that original regulator ended up being unstable. Reading papers on stability led to another design that was more stable but initially wouldn’t regulate to the correct voltage because the feedback was not being used properly. Further research helped us adapt the design to the 0.5 µm technology we used. Once we achieved proper regulating we looked at our ripple rejection which at that point was 20 dB. By reading more papers on stabilization and regulator design we discovered that the output impedance is really the only parameter that a designer can change to improve their ripple rejection. Previously we had the output impedance be as small as possible; by increasing it, we were able to achieve a ripple rejection of 66.3 dB. The accuracy of our regulator now depended on our voltage reference.
The voltage reference had to be generated in such a way that it was stable and mostly independent of temperature. Lots of time spent in books led us to lateral BJT voltage reference designs. The lateral BJT ended up being too difficult for us to extract and correctly use in Cadence, so we settled for a similar design we found using the bandgap in a MOSFET. Instead of the normal 1.25 V bandgap, ours put out 0.9 V, which wasn’t a problem because we just had to adjust two resistors in the voltage regulator to correctly use 0.9 V.
Figure : Rectifier schematic
Figure : Rectifier response to a 2 V peak-to-peak input
The rectifier converts the square wave input into two DC waves. This is achieved by selecting which wave is high at any given time and using that as the high output and the same for the low output. We accomplish this with only 4 transistors. The variation on the output at the switching frequency is negligible. Figure 3 shows the output of the rectifier with a 2 Vpp input. As shown, the difference between the positive and negative outputs is within 2 mV of 2 V, giving a very efficient rectification.
In order to reach the desired output of 1.8 V, the main line voltage had to be raised from its input level. The voltage multiplier ideally outputs double the input voltage. This is accomplished by using a switch capacitor, which allows us to have relatively high current output as well as increased voltage. The circuit uses two clocks to operate the switching. Figure 5 is the output of the voltage multiplier with a 2 V input and 3.9 V control signals. We tested with those values because they illustrate the lower end values at the inputs. It is shown that the voltage multiplier increases the voltage by a factor of 1.9. This component is the least efficient part of the design because of the capacitor losses and the greatest power loss overall.
Figure : Voltage Multiplier schematic
Figure : Voltage Multiplier test showing the output to a 2 V input. The output boosts the input by a factor of 1.9
The charge pump provides the necessary increase in
voltage for the clocks of the voltage doubler. To operate correctly, the
clocks into the voltage doubler had to be boosted to a higher voltage than the
output in order for the transistors to function. This was done with a
charge pump design that pushes charge through eight capacitors, multiplying the
voltage by four. The small capacitors we used cause the component to only
function under low current draw, but this works for our design because ideally
zero current would flow through the clocks. Figure 7 demonstrates the output of
the charge pump at 2 Vpp. The output is boosted to 5 V, which is
sufficient for the control signals of the voltage multiplier.
Figure : Charge Pump schematic
Figure : Charge pump output to a 2 V input. The output is boosted to roughly 5 V, which will be high enough to control the voltage multiplier.
This part generates a stable output at roughly 0.9
V used in the voltage regulator. The characteristic drop across a MOSFET is used
along with a current mirror to provide a stable reference for output. The
output changes slightly with temperature, but not enough to make a significant
difference at normal operating points. Figure 9 is a test of the
voltage reference from 0º-35º C. The output varies from slightly below
0.9 to just above at 35º, the maximum operating temperature of most
Figure : Voltage Reference schematic
Figure : Voltage reference output over 0 to 35 Celsius. The output varies slightly, but is approximately 0.9 V
This part takes in a wave
always greater than 2.2 V and returns a stable 1.8 V DC wave. It is the
final part in the main current flow. The circuit works by comparing the
output to a reference voltage of 0.9 V and adjusting a pass transistor
accordingly until the output is at the right level. The desired output
voltage is changed by tweaking the two output resistors. The regulator
works by feedback to a comparator and then small changes until 1.8 V is
achieved. Stability was a large concern so we had to implement
compensation circuitry to slowdown the feedback process. Using this method
we achieved 66.3 dB of ripple reduction so that the output is incredibly stable.
Figures 11 and 12 display the operating characteristics of the voltage
regulator. Figure 11 demonstrates the requirements for the input voltage
of the voltage regulator. We found that we could regulate down to 1.8 V if
the input was at least 2.2 V, and that the output would stay at 1.8 V up to at
least 5 V. Figure 12 shows the ripple reduction of the voltage regulator;
when the input swings 1 V, the output changes less than 1 mV.
Figure : Voltage Regulator schematic
Figure : Range of operation for the voltage regulator. Operates correctly above 2.2 V
Figure : Output of the voltage regulator with a varying input showing ripple rejection of the voltage regulator. Achieves 66.3 dB of ripple rejection.
The overall block diagram shows how all the parts connect to form the final product. In addition to the five parts described, there are three inverters which act as amplifiers for clock signals to the voltage doubler. The majority of current will flow from the power source through the rectifier to the voltage doubler and into the voltage regulator. Figure 14 shows the outputs of the voltage regulator, voltage multiplier, and rectifier when all connected with a load. As seen at the output of the voltage regulator, the design meets the specification of 1.8 V.
Figure : Overall block diagram
Figure : Output of the main parts in the overall block diagram under normal operating conditions.
Cost per Unit
*Cost derived from assuming a .95 packing efficiency, .8 yield efficiency, and a 12” wafer.
We designed an ASIC CMOS circuit to use a smartphone’s audio output to power an integrated circuit at 1.8 V and 2 mA in the ami0.6 process that functions across a wide variety of phones. The design fits on a 1mm2 die and we were able to achieve an overall efficiency of 37.3%. The vast majority of our time we spent trying to understand a voltage regulator. However at this point the weakness in the design is the Voltage Multiplier. It is where we take our highest power losses, and if we had more time is what we would focus on next.
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